mailRe: [Ghdl-discuss] ghdl 0.26 and Xilinx SIMPRIM library


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Posted by Walter F.J. Mueller on October 15, 2007 - 20:48:
Kees Bakker wrote:
I don't know about your split utility. All I can say is that I have to 
apply the following
patch to compile unisim_VITAL.vhd. The same lines occur in 
simprim_VITAL.vhd as well.

This is a quite minimal perl script to splitt the file at module boundaries.
It uses the CVS headers in the XILINX files are marker. The script is
attached in case somebody likes it. It is used by two shell scripts used
to compile UNISIM and SIMPRIM and put the ghdl compiled lib's under
   $XILINX/ghdl/unisim   and   $XILINX/ghdl/simprim
They are also appended, in case somebody finds them usefull.

--- unisims/unisim_VITAL.vhd~ 2005-02-09 14:52:03.000000000 +0100
+++ unisims/unisim_VITAL.vhd  2007-06-22 10:55:41.617061000 +0200
@@ -145286,12 +145286,12 @@
 
     variable collision_msg   : memory_collision_type;
 
-    variable Write_A_Write_B : memory_collision_type := Write_A_Write_B;
-    variable Read_A_Write_B  : memory_collision_type := Read_A_Write_B;
-    variable Write_A_Read_B  : memory_collision_type := Write_A_Read_B;
-    variable Write_B_Write_A : memory_collision_type := Write_B_Write_A;
-    variable Read_B_Write_A  : memory_collision_type := Read_B_Write_A;
-    variable Write_B_Read_A  : memory_collision_type := Write_B_Read_A;
+--    variable Write_A_Write_B : memory_collision_type := Write_A_Write_B;
+--    variable Read_A_Write_B  : memory_collision_type := Read_A_Write_B;
+--    variable Write_A_Read_B  : memory_collision_type := Write_A_Read_B;
+--    variable Write_B_Write_A : memory_collision_type := Write_B_Write_A;
+--    variable Read_B_Write_A  : memory_collision_type := Read_B_Write_A;
+--    variable Write_B_Read_A  : memory_collision_type := Write_B_Read_A;
 
     variable msg_addr1       : std_logic_vector(MAX_ADDR downto 0)      := 
(others => '0');
     variable msg_addr2       : std_logic_vector(MAX_ADDR downto 0)      := 
(others => '0');

Dear Kees,

I'm aware of these variable declarations, with a non-sensical self-referencial
initialization. They are indeed in some of the files which end with a
compilation error, but not in all of them. The modules x_aramb36_internal.vhd
or x_ramb4_s1.vhd for example have no such inits. I get a bunch of warnings,
and finally a

  ghdl: compilation error

without a further statement on what went wrong. Removing the bad variable
declarations in other actually doesn't help, tried this with x_srlc32e.vhd .

                        With best regards,

                                Walter

-- 
Dr. Walter F.J. Müller       Mail:  W.F.J.Mueller@xxxxxx
GSI,  Abteilung KP3          Phone: +49-6159-71-2766
Planckstr. 1                 FAX:   +49-6159-71-3762
D-64291 Darmstadt            URL: http://www-linux.gsi.de/~mueller/

-------------------------------------------------------------------------------
--- xilinx_vhdl_chop 
----------------------------------------------------------
-------------------------------------------------------------------------------
#!/usr/bin/perl -w
# $Id: xilinx_vhdl_chop 87 2007-10-06 15:21:26Z mueller $
#
# Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@xxxxxx>
#
# This program is free software; you may redistribute and/or modify it under
# the terms of the GNU General Public License Version 2 as published by the
# Free Software Foundation.
#
# This program is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
# or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
# for complete details.
#
#
# splits a xilinx unisim_VITAL.vhd file along separators looking like:
#
#   -- $Header: <path>/and5b1.vhd,v 1.4 2004/04/08 18:46:23 patrickp Exp $
#

use 5.003;                                  # require Perl 5.003 or higher
use strict;                                 # require strict checking

while (<>) {
  chomp;
  my @line = split;
  if (/^-- \$Header/) {
    my @file = split(/\//,$line[2]);
    my $name = $file[$#file];
    $name =~ s/,v//;
    print "writing $name \n";
    close(OFILE);
    open(OFILE, "> $name") or die "Couldn't open output file: $!\n";
  }
  print OFILE $_,"\n";
}
close(OFILE);

-------------------------------------------------------------------------------
--- xilinx_ghdl_unisim 
--------------------------------------------------------
-------------------------------------------------------------------------------
#!/bin/sh
# $Id: xilinx_ghdl_unisim 88 2007-10-12 20:37:45Z mueller $
#
if [ -z "$XILINX" ]
then
  echo "XILINX not defined"
  exit 1
fi
#
cd $XILINX
echo "============================================================"
echo "* Build ghdl UNISIM libs for $XILINX"
echo "============================================================"
#
if [ ! -d ghdl ]
then
  mkdir ghdl
fi
#
cd $XILINX/ghdl
if [ ! -d unisim  ]
then
  mkdir unisim
fi
#
cd $XILINX/ghdl/unisim
cp $XILINX/vhdl/src/unisims/unisim_VCOMP.vhd .
cp $XILINX/vhdl/src/unisims/unisim_VPKG.vhd .
#
if [ ! -d unisim_vital_chop  ]
then
  mkdir unisim_vital_chop
fi
cd unisim_vital_chop
xilinx_vhdl_chop $XILINX/vhdl/src/unisims/unisim_VITAL.vhd
#
cd ..
echo "# ghdl ... unisim_VCOMP.vhd"
ghdl -a --ieee=synopsys --work=unisim unisim_VCOMP.vhd
echo "# ghdl ... unisim_VPKG.vhd"
ghdl -a --ieee=synopsys --work=unisim unisim_VPKG.vhd

for file in `find unisim_vital_chop -name "*.vhd"`
do
  echo "# ghdl ... $file"
  ghdl -a -fexplicit --ieee=synopsys --work=unisim 2>&1 $file |\
      tee $file.ghdl.log
done
#
echo "--- scan for compilation errors:"
find unisim_vital_chop -name "*.ghdl.log" | xargs grep error
#

-------------------------------------------------------------------------------
--- xilinx_ghdl_simprim 
-------------------------------------------------------
-------------------------------------------------------------------------------
#!/bin/sh
# $Id: xilinx_ghdl_simprim 88 2007-10-12 20:37:45Z mueller $
#
if [ -z "$XILINX" ]
then
  echo "XILINX not defined"
  exit 1
fi
#
cd $XILINX
echo "============================================================"
echo "* Build ghdl SIMPRIM libs for $XILINX"
echo "============================================================"
#
if [ ! -d ghdl ]
then
  mkdir ghdl
fi
#
cd $XILINX/ghdl
if [ ! -d simprim  ]
then
  mkdir simprim
fi
#
cd $XILINX/ghdl/simprim
cp $XILINX/vhdl/src/simprims/simprim_Vcomponents.vhd .
cp $XILINX/vhdl/src/simprims/simprim_Vpackage.vhd .
#
if [ ! -d simprim_vital_chop  ]
then
  mkdir simprim_vital_chop
fi
cd simprim_vital_chop
xilinx_vhdl_chop $XILINX/vhdl/src/simprims/simprim_VITAL.vhd
#
cd ..
echo "# ghdl ... simprim_Vcomponents.vhd"
ghdl -a --ieee=synopsys --work=simprim simprim_Vcomponents.vhd
echo "# ghdl ... simprim_Vpackage.vhd"
ghdl -a --ieee=synopsys --work=simprim simprim_Vpackage.vhd

for file in `find simprim_vital_chop -name "*.vhd"`
do
  echo "# ghdl ... $file"
  ghdl -a -fexplicit --ieee=synopsys --work=simprim 2>&1 $file |\
      tee $file.ghdl.log
done
#
echo "--- scan for compilation errors:"
find simprim_vital_chop -name "*.ghdl.log" | xargs grep error
#



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